A semiconductor memory device includes a cell array having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between the plurality of first wirings and the plurality of second wirings. The semiconductor memory device further includes a control circuit for selectively driving the plurality of first wirings and the plurality of second wirings. The control circuit applies a first voltage for a first operation to a first select wiring and applies a second voltage for a second operation different from the first operation to a second select wiring and applies a third voltage for the first and second operation to a third select wiring. The first operation is completed before the second operation is completed. The control circuit applies a fourth voltage for a third operation to a forth select wiring before the second operation is completed.