A semiconductor memory device includes a voltage generator configured to supply a program voltage, a sub-verification voltage, or a target verification voltage to memory cells selected during a program operation, page buffers configured to latch first data according to results from comparing threshold voltages of the selected memory cells with the sub-verification voltage and latch second data according to results from comparing the threshold voltages of the memory cells with the target verification voltage, a sub-pass check circuit configured to output a sub-pass signal in response to the first data outputted from the page buffers, a main pass check circuit configured to output a main pass signal in response to the second data outputted from the page buffers, and a control circuit configured to control whether the voltage generator supplies the sub-verification voltage and the target verification voltage in response to the sub-pass signal and the main pass signal.