A semiconductor memory device operate during a program verification operation to apply a read voltage to a word line and a pre-charge voltage to a bit line in order to provide output data. A number of fail cells is determined in view of the output data, wherein the number of fail cells is directly related to an increase in voltage on a common source line (CSL) connected to memory cells providing the output data. During a subsequent program verification operation, the level of at least one of the read voltage and the pre-charge voltage is adjusted in response to the number of fail cells.