Provided is a signal processing apparatus including an encoder for encoding, according to respective specific coding schemes, a first bit string formed from bit values at odd-numbered positions and a second bit string formed from bit values at even-numbered positions that are obtained by alternately extracting bit values from a bit string that is expressed by mutually different first and second bit values, and generating first and second encoded signals that do not include a DC component, and a signal generation unit for generating a multilevel signal by respectively adding, to a clock signal having larger amplitude than the first and second encoded signals that are generated by the encoder, the first encoded signal in synchronization with a timing of the clock signal being at a positive amplitude value and the second encoded signal in synchronization with a timing of the clock signal being at a negative amplitude value.