Invention Grant
- Patent Title: Phase locked loop, CDR circuit, and receiving circuit
- Patent Title (中): 锁相环,CDR电路和接收电路
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Application No.: US13180620Application Date: 2011-07-12
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Publication No.: US08625730B2Publication Date: 2014-01-07
- Inventor: Tatsunori Usugi , Daisuke Hamano
- Applicant: Tatsunori Usugi , Daisuke Hamano
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2010-195282 20100901
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.
Public/Granted literature
- US20120051480A1 PHASE LOCKED LOOP, CDR CIRCUIT, AND RECEIVING CIRCUIT Public/Granted day:2012-03-01
Information query
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