Invention Grant
- Patent Title: Memory model for hardware attributes within a transactional memory system
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Application No.: US12346539Application Date: 2008-12-30
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Publication No.: US08627014B2Publication Date: 2014-01-07
- Inventor: Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
- Applicant: Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
Public/Granted literature
- US20100169580A1 MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM Public/Granted day:2010-07-01
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