A device under test (DUT) is tested by: receiving a signal transmitted by the DUT, wherein the signal includes first portions that include scrambled bits produced from a selected bit pattern and a selected scrambling algorithm, and further includes second portions that include unscrambled bits, the first portions and second portions being interspersed within the signal; detecting received scrambled bits within the received signal; generating a test bit sequence using the selected scrambling algorithm and the selected bit pattern, including generating a bit of the test bit sequence for each of the received scrambled bits within the received signal, and not generating a bit of the test bit sequence for each of the received unscrambled bits within the received signal; and comparing the received scrambled bits to the test bit sequence to determine a bit error rate of the received signal.