Invention Grant
- Patent Title: Feedback scan isolation and scan bypass architecture
- Patent Title (中): 反馈扫描隔离和扫描旁路架构
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Application No.: US12944090Application Date: 2010-11-11
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Publication No.: US08627159B2Publication Date: 2014-01-07
- Inventor: Paul F. Policke , Kim S. Hong , Paul Douglas Bassett
- Applicant: Paul F. Policke , Kim S. Hong , Paul Douglas Bassett
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter Michael Kamarchik; Nicholas J. Pauley; Joseph Agusta
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.
Public/Granted literature
- US20120124433A1 Feedback Scan Isolation and Scan Bypass Architecture Public/Granted day:2012-05-17
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