Invention Grant
US08627172B2 Error correction encoding apparatus, decoding apparatus, encoding method, decoding method, and programs thereof 有权
纠错编码装置,解码装置,编码方法,解码方法及程序

  • Patent Title: Error correction encoding apparatus, decoding apparatus, encoding method, decoding method, and programs thereof
  • Patent Title (中): 纠错编码装置,解码装置,编码方法,解码方法及程序
  • Application No.: US13139785
    Application Date: 2009-12-11
  • Publication No.: US08627172B2
    Publication Date: 2014-01-07
  • Inventor: Norifumi Kamiya
  • Applicant: Norifumi Kamiya
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2008-330910 20081225
  • International Application: PCT/JP2009/070756 WO 20091211
  • International Announcement: WO2010/073922 WO 20100701
  • Main IPC: H03M13/00
  • IPC: H03M13/00
Error correction encoding apparatus, decoding apparatus, encoding method, decoding method, and programs thereof
Abstract:
Provided is an encoding apparatus wherein a transmission data sequence is divided into L short sequences, each of which is then encoded by use of an m-stage pseudo-cyclic low-density parity check encoding system. Each of the L encoded sequences is further divided into shorter sequences, the number of which is identical to the number m of the stages of the pseudo-cyclic codes and each of which has a length m. The shorter sequences are rearranged in order by a replacing module, thereafter encoded, by use of the m-stage pseudo-cyclic low-density parity check encoding system, and outputted. Accordingly, a decoding apparatus with a simple structure where node processing circuits (e.g., minimum-value calculating circuits), the number of which is p that is a submultiple of the number m of the foregoing stages, are provided, can be employed to efficiently decode the codes having a large frame length and a large encoding gain.
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