Invention Grant
US08627188B2 Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
有权
使用多个解码级的闪存装置和方法，包括可选地使用级联的BCH码和/或“第一低于”小区的指定
- Patent Title: Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
- Patent Title (中): 使用多个解码级的闪存装置和方法，包括可选地使用级联的BCH码和/或“第一低于”小区的指定
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Application No.: US13708432Application Date: 2012-12-07
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Publication No.: US08627188B2Publication Date: 2014-01-07
- Inventor: Hanan Weingarten , Shmuel Levy , Michael Katz
- Applicant: Hanan Weingarten , Shmuel Levy , Michael Katz
- Applicant Address: IL Haifa
- Assignee: Densbits Technologies Ltd.
- Current Assignee: Densbits Technologies Ltd.
- Current Assignee Address: IL Haifa
- Agency: Dentons US LLP
- Main IPC: H03M13/03
- IPC: H03M13/03
Abstract:
A method for decoding a plurality of flash memory cells which are error correction-coded, the method may include: comparing physical values residing in the plurality of flash memory cells to a first set of decision thresholds thereby to provide a first item of comparison information for each of the plurality of cells; comparing physical values residing the plurality of flash memory cells to a second set of decision thresholds, thereby to provide a second item of comparison information for each of the plurality of cells, wherein neither of the first and second sets of decision thresholds is a subset of the other; and determining logical values for the plurality of flash memory cells by combining said first and second items of comparison information.
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