Invention Grant
- Patent Title: Automatic generation of merged mode constraints for electronic circuits
- Patent Title (中): 自动生成电子电路的合并模式约束
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Application No.: US12960745Application Date: 2010-12-06
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Publication No.: US08627262B2Publication Date: 2014-01-07
- Inventor: Subramanyam Sripada , Sonia Singhal , Cho Moon
- Applicant: Subramanyam Sripada , Sonia Singhal , Cho Moon
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.
Public/Granted literature
- US20110252393A1 AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS Public/Granted day:2011-10-13
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