Invention Grant
US08633756B2 Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling common mode voltage at input
有权
低压差分信号（LVDS）电路和方法，用于动态控制输入端的共模电压
- Patent Title: Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling common mode voltage at input
- Patent Title (中): 低压差分信号（LVDS）电路和方法，用于动态控制输入端的共模电压
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Application No.: US13188194Application Date: 2011-07-21
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Publication No.: US08633756B2Publication Date: 2014-01-21
- Inventor: Arlo J. Aude , Soumya Chandramouli
- Applicant: Arlo J. Aude , Soumya Chandramouli
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Andrew Viger; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03L5/00
- IPC: H03L5/00
Abstract:
Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.
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