Invention Grant
- Patent Title: Redundancy in column parallel or row architectures
- Patent Title (中): 列平行或行架构的冗余
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Application No.: US13865521Application Date: 2013-04-18
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Publication No.: US08634010B2Publication Date: 2014-01-21
- Inventor: Christian Boemler
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dickstein Shapiro LLP
- Main IPC: H04N5/335
- IPC: H04N5/335 ; H04N5/217 ; H04N9/64 ; H01L31/113 ; H01L27/00

Abstract:
A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row circuits. Each column or row circuit include circuitry for controllably coupling the column or row circuit to one of plural signal lines from an array of pixels. A control mechanism is used to select a configuration of plural column or row circuits in the column or row circuitry. In this manner, some column or row circuits are decoupled from the pixel in favor of other column or row circuits. The decoupled column or row circuits may include defective or noisy circuits.
Public/Granted literature
- US20130229559A1 REDUNDANCY IN COLUMN PARALLEL OR ROW ARCHITECTURES Public/Granted day:2013-09-05
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