Invention Grant
US08634221B2 Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method
有权
利用宽输入/输出（I / O）接口将存储器存储与内插器进行接口并利用SerDes接口将存储器控制器与集成电路连接的存储器系统，以及一种方法
- Patent Title: Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method
- Patent Title (中): 利用宽输入/输出（I / O）接口将存储器存储与内插器进行接口并利用SerDes接口将存储器控制器与集成电路连接的存储器系统，以及一种方法
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Application No.: US13286338Application Date: 2011-11-01
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Publication No.: US08634221B2Publication Date: 2014-01-21
- Inventor: Larry J. Thayer
- Applicant: Larry J. Thayer
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: G11C5/04
- IPC: G11C5/04
Abstract:
A memory system is provided in which at least one DRAM chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The DRAM chip is connected to the interposer via a Wide I/O interface to enable the DRAM chip and the memory controller chip to communicate with each other via the Wide I/O interface. The memory controller chip has a SerDes interface for communicating with a SerDes interface of an integrated circuit (IC) chip of the memory system.
Public/Granted literature
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