A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver.