Invention Grant
US08634550B2 Architecture and instruction set for implementing advanced encryption standard (AES)
有权
实现高级加密标准（AES）的体系结构和指令集
- Patent Title: Architecture and instruction set for implementing advanced encryption standard (AES)
- Patent Title (中): 实现高级加密标准（AES）的体系结构和指令集
-
Application No.: US13088088Application Date: 2011-04-15
-
Publication No.: US08634550B2Publication Date: 2014-01-21
- Inventor: Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
- Applicant: Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Christopher K. Gagne
- Main IPC: H04L9/28
- IPC: H04L9/28 ; G06F15/00 ; G06F12/14
Abstract:
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
Public/Granted literature
- US20120002804A1 ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) Public/Granted day:2012-01-05
Information query
