Invention Grant
US08635408B2 Controlling power of a cache based on predicting the instruction cache way for high power applications
有权
基于预测大功率应用的指令高速缓存方式来控制高速缓存的功率
- Patent Title: Controlling power of a cache based on predicting the instruction cache way for high power applications
- Patent Title (中): 基于预测大功率应用的指令高速缓存方式来控制高速缓存的功率
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Application No.: US12984300Application Date: 2011-01-04
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Publication No.: US08635408B2Publication Date: 2014-01-21
- Inventor: Sheldon B. Levenstein , David S. Levitan
- Applicant: Sheldon B. Levenstein , David S. Levitan
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen J. Walder, Jr.; Matthew B. Talpis
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code. During the first execution of the portion of code, information identifying which cache lines in the cache memory are accessed during the execution of the portion of code is stored in a storage device of the data processing system. Subsequently, during a second execution of the portion of code, power to the cache memory is controlled such that only the cache lines that were accessed during the first execution of the portion of code are powered-up.
Public/Granted literature
- US20120173821A1 Predicting the Instruction Cache Way for High Power Applications Public/Granted day:2012-07-05
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