Invention Grant
US08637362B2 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
有权
具有超薄蚀刻柱环绕栅极存取晶体管和埋地数据/位线的存储阵列
- Patent Title: Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
- Patent Title (中): 具有超薄蚀刻柱环绕栅极存取晶体管和埋地数据/位线的存储阵列
-
Application No.: US13548614Application Date: 2012-07-13
-
Publication No.: US08637362B2Publication Date: 2014-01-28
- Inventor: Leonard Forbes
- Applicant: Leonard Forbes
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H01L29/72
- IPC: H01L29/72
Abstract:
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.
Public/Granted literature
- US20120276699A1 MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES Public/Granted day:2012-11-01
Information query
IPC分类:
