Invention Grant
- Patent Title: FinFET parasitic capacitance reduction using air gap
- Patent Title (中): 使用气隙对FinFET寄生电容进行减小
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Application No.: US13617426Application Date: 2012-09-14
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Publication No.: US08637384B2Publication Date: 2014-01-28
- Inventor: Takashi Ando , Josephine B. Chang , Sivananda K. Kanakasabapathy , Pranita Kulkarni , Theodorus E. Standaert , Tenko Yamashita
- Applicant: Takashi Ando , Josephine B. Chang , Sivananda K. Kanakasabapathy , Pranita Kulkarni , Theodorus E. Standaert , Tenko Yamashita
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Harrington & Smith
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/283

Abstract:
Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.
Public/Granted literature
- US20130095629A1 Finfet Parasitic Capacitance Reduction Using Air Gap Public/Granted day:2013-04-18
Information query
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