Invention Grant
- Patent Title: Semiconductor apparatus and method of trimming voltage
- Patent Title (中): 半导体装置及修整电压的方法
-
Application No.: US12966706Application Date: 2010-12-13
-
Publication No.: US08638006B2Publication Date: 2014-01-28
- Inventor: Jae Hyuk Im
- Applicant: Jae Hyuk Im
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd
- Priority: KR10-2010-0106804 20101029
- Main IPC: H02J1/10
- IPC: H02J1/10

Abstract:
A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage.
Public/Granted literature
- US20120105142A1 SEMICONDUCTOR APPARATUS AND METHOD OF TRIMMING VOLTAGE Public/Granted day:2012-05-03
Information query