Invention Grant
- Patent Title: Analog/digital partitioning of circuit designs for simulation
- Patent Title (中): 用于模拟的电路设计的模拟/数字分区
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Application No.: US13898007Application Date: 2013-05-20
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Publication No.: US08640073B2Publication Date: 2014-01-28
- Inventor: Chandrashekar L. Chetput , Abhijeet Kolpekwar , Iyengar Srinivasan
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.
Public/Granted literature
- US20130326440A1 ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION Public/Granted day:2013-12-05
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