Invention Grant
- Patent Title: Method of manufacturing a semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US13315060Application Date: 2011-12-08
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Publication No.: US08642422B2Publication Date: 2014-02-04
- Inventor: Koji Shimbayashi
- Applicant: Koji Shimbayashi
- Applicant Address: US CA Sunnyvale
- Assignee: Spansion LLC
- Current Assignee: Spansion LLC
- Current Assignee Address: US CA Sunnyvale
- Main IPC: H01L21/8242
- IPC: H01L21/8242

Abstract:
In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate, layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
Public/Granted literature
- US20120309146A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2012-12-06
Information query
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