Invention Grant
- Patent Title: Thin film transistor having a patterned passivation layer
- Patent Title (中): 具有图案化钝化层的薄膜晶体管
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Application No.: US13163727Application Date: 2011-06-20
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Publication No.: US08643006B2Publication Date: 2014-02-04
- Inventor: Chia-Hsiang Chen , Ming-Chin Hung , Chun-Hao Tu , Wei-Ting Lin , Jiun-Jye Chang
- Applicant: Chia-Hsiang Chen , Ming-Chin Hung , Chun-Hao Tu , Wei-Ting Lin , Jiun-Jye Chang
- Applicant Address: TW Hsinchu
- Assignee: Au Optronics Corporation
- Current Assignee: Au Optronics Corporation
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW100114110A 20110422
- Main IPC: H01L29/786
- IPC: H01L29/786

Abstract:
A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.
Public/Granted literature
- US20120267621A1 THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF Public/Granted day:2012-10-25
Information query
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