Invention Grant
- Patent Title: Reduced leakage memory cells
- Patent Title (中): 减少泄漏记忆体
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Application No.: US11524343Application Date: 2006-09-20
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Publication No.: US08643087B2Publication Date: 2014-02-04
- Inventor: Gurtej S. Sandhu , Chandra Mouli
- Applicant: Gurtej S. Sandhu , Chandra Mouli
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L29/10
- IPC: H01L29/10

Abstract:
Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.
Public/Granted literature
- US20080068876A1 Reduced leakage memory cells Public/Granted day:2008-03-20
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