Invention Grant
US08643092B2 Shielded trench MOSFET with multiple trenched floating gates as termination
有权
具有多个沟槽浮动栅极的屏蔽沟槽MOSFET作为端接
- Patent Title: Shielded trench MOSFET with multiple trenched floating gates as termination
- Patent Title (中): 具有多个沟槽浮动栅极的屏蔽沟槽MOSFET作为端接
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Application No.: US13169323Application Date: 2011-06-27
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Publication No.: US08643092B2Publication Date: 2014-02-04
- Inventor: Fu-Yuan Hsieh
- Applicant: Fu-Yuan Hsieh
- Applicant Address: TW New Taipei
- Assignee: Force Mos Technology Co., Ltd.
- Current Assignee: Force Mos Technology Co., Ltd.
- Current Assignee Address: TW New Taipei
- Agency: Bacon & Thomas, PLLC
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94

Abstract:
A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.
Public/Granted literature
- US20110254086A1 SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION Public/Granted day:2011-10-20
Information query
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