Invention Grant
- Patent Title: Capacitor array layout arrangement for high matching methodology
- Patent Title (中): 高匹配方法的电容阵列布局布置
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Application No.: US13602471Application Date: 2012-09-04
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Publication No.: US08643141B2Publication Date: 2014-02-04
- Inventor: Chung-Ting Lu , Chih-Chiang Chang
- Applicant: Chung-Ting Lu , Chih-Chiang Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/20

Abstract:
Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed.
Public/Granted literature
- US20130270671A1 Capacitor Array Layout Arrangement for High Matching Methodology Public/Granted day:2013-10-17
Information query
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