Invention Grant
- Patent Title: Processed wafer via
- Patent Title (中): 加工晶片通孔
-
Application No.: US12846495Application Date: 2010-07-29
-
Publication No.: US08643186B2Publication Date: 2014-02-04
- Inventor: John Trezza
- Applicant: John Trezza
- Applicant Address: US DE Wilmington
- Assignee: Cufer Asset Ltd. L.L.C.
- Current Assignee: Cufer Asset Ltd. L.L.C.
- Current Assignee Address: US DE Wilmington
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L27/148 ; H01L21/4763 ; H01L21/44

Abstract:
An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.
Public/Granted literature
- US20100304565A1 PROCESSED WAFER VIA Public/Granted day:2010-12-02
Information query
IPC分类: