Invention Grant
US08643413B2 Semiconductor device using multi-phase clock signal and information processing system including the same 有权
半导体器件采用多相时钟信号和信息处理系统,包括相同的

Semiconductor device using multi-phase clock signal and information processing system including the same
Abstract:
Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
Information query
Patent Agency Ranking
0/0