There is provided a semiconductor memory device having a plurality of memory cell layers which can be used even if part of the memory cell layers is determined as defective. The semiconductor memory device includes a stacked memory cell array having a laminated plurality of memory cell layers, each of which has a plurality of blocks; a layer quality information storing circuit (10) which can store layer quality information indicating whether the individual memory cell layer is a normal memory cell layer or a defective memory cell layer so as to identify a memory cell layer in which the number of defective blocks found is equal to or greater than a predetermined number as a defective memory cell layer and the other memory cell layers as normal memory cell layers; and address converting circuit (11) in which if an externally input address input from outside corresponds to the block in the defective memory cell layer, the externally input address is address-converted so as to correspond to the block of the normal memory cell layer.