Invention Grant
- Patent Title: Writing circuit, semiconductor integrated circuit and writing method
- Patent Title (中): 写电路,半导体集成电路和写入方式
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Application No.: US13465096Application Date: 2012-05-07
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Publication No.: US08644093B2Publication Date: 2014-02-04
- Inventor: Takahisa Hiraide
- Applicant: Takahisa Hiraide
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2011-174318 20110809
- Main IPC: G11C7/06
- IPC: G11C7/06 ; G11C7/22 ; G11C17/00

Abstract:
A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data the OTP macro stores; and a comparator to compare the data read from the OTP macro in response to the second signal with the data stored in the storage and output a comparison result, wherein the controller ends a process associated with the writing data if the comparison result indicates a match, and applies the first and second signals again if the comparison result indicates a mismatch.
Public/Granted literature
- US20130039114A1 WRITING CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND WRITING METHOD Public/Granted day:2013-02-14
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