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US08644447B2 System and a method for generating time bases in low power domain 有权
在低功率域中生成时基的系统和方法

System and a method for generating time bases in low power domain
Abstract:
A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.
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