Invention Grant
- Patent Title: Agile clocking with receiver PLL management
- Patent Title (中): 具有接收机PLL管理的敏捷时钟
-
Application No.: US13435033Application Date: 2012-03-30
-
Publication No.: US08644782B2Publication Date: 2014-02-04
- Inventor: Brijesh Tripathi , Timothy J. Millet
- Applicant: Brijesh Tripathi , Timothy J. Millet
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Lawrence J. Merkel
- Main IPC: H04B7/00
- IPC: H04B7/00

Abstract:
A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.
Public/Granted literature
- US20130120037A1 Agile Clocking with Receiver PLL Management Public/Granted day:2013-05-16
Information query