Invention Grant
US08645633B2 Facilitating data coherency using in-memory tag bits and faulting stores
有权
使用内存中标记位和故障存储来促进数据一致性
- Patent Title: Facilitating data coherency using in-memory tag bits and faulting stores
- Patent Title (中): 使用内存中标记位和故障存储来促进数据一致性
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Application No.: US13109249Application Date: 2011-05-17
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Publication No.: US08645633B2Publication Date: 2014-02-04
- Inventor: Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
- Applicant: Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent Steven Chiu, Esq.; Kevin P. Radigan, Esq.
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.
Public/Granted literature
- US20120297109A1 FACILITATING DATA COHERENCY USING IN-MEMORY TAG BITS AND FAULTING STORES Public/Granted day:2012-11-22
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