Invention Grant
- Patent Title: Integrated circuit power management verification method
- Patent Title (中): 集成电路电源管理验证方法
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Application No.: US13447305Application Date: 2012-04-16
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Publication No.: US08645886B2Publication Date: 2014-02-04
- Inventor: Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
- Applicant: Kumar Abhishek , Benjamin J. Ehlers , Sunny Gupta , Stefano Pietri
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F17/10
Abstract:
A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value.
Public/Granted literature
- US20130275936A1 INTEGRATED CIRCUIT POWER MANAGEMENT VERIFICATION METHOD Public/Granted day:2013-10-17
Information query
