Invention Grant
- Patent Title: Checking an ESD behavior of integrated circuits on the circuit level
- Patent Title (中): 检查电路级集成电路的ESD特性
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Application No.: US12742956Application Date: 2008-12-04
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Publication No.: US08645895B2Publication Date: 2014-02-04
- Inventor: Lars Bergmann , Angela Konrad , Markus Frank
- Applicant: Lars Bergmann , Angela Konrad , Markus Frank
- Applicant Address: DE Erfurt
- Assignee: X-Fab Semiconductor Foundries AG
- Current Assignee: X-Fab Semiconductor Foundries AG
- Current Assignee Address: DE Erfurt
- Agency: Duane Morris LLP
- Priority: EP07122324 20071204
- International Application: PCT/EP2008/066838 WO 20081204
- International Announcement: WO2009/071646 WO 20090611
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A system and a method for testing the ESD behavior, wherein a circuit (7) is automatically tested at circuit diagram level in that technology-specific ESD data is provided in database (2) for each circuit component present in the circuit, without requiring complex circuit simulations, for example based on front end or back end data, by taking into account the layout.
Public/Granted literature
- US20110016440A1 CHECKING AN ESD BEHAVIOR OF INTEGRATED CIRCUITS ON THE CIRCUIT LEVEL Public/Granted day:2011-01-20
Information query
