Semiconductor device and semiconductor device manufacturing method

Invention Grant

US08647944B2 Semiconductor device and semiconductor device manufacturing method 有权

Title translation: 半导体器件和半导体器件制造方法

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Patent Title: Semiconductor device and semiconductor device manufacturing method
Patent Title (中): 半导体器件和半导体器件制造方法
Application No.: US13927855

Application Date: 2013-06-26
Publication No.: US08647944B2

Publication Date: 2014-02-11
Inventor: Hiroki Shinkawata
Applicant: Renesas Electronics Corporation
Applicant Address: JP Kawasaki-shi
Assignee: Renesas Electronics Corporation
Current Assignee: Renesas Electronics Corporation
Current Assignee Address: JP Kawasaki-shi
Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
Priority: JP2003-044155 20030221; JP2003-345633 20031003
Main IPC: H01L21/8242
IPC: H01L21/8242

Semiconductor device and semiconductor device manufacturing method

Abstract:

A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.

Abstract(Chinese):

一种半导体器件，包括具有形成逻辑器件的逻辑形成区域的半导体衬底; 形成在所述逻辑形成区域中的所述半导体衬底的上表面中的第一杂质区; 形成在所述逻辑形成区域中的所述半导体衬底的上表面中的第二杂质区; 第三杂质区，形成在所述第一杂质区的上表面，并且具有不同于所述第二杂质区的导电型; 第四区域，形成在所述第二杂质区域的上表面中，并且具有不同于所述第二杂质区域的导电型; 形成在第三杂质区的上表面的第一硅化物膜; 形成在所述第四杂质区的上表面中并且具有比所述第一硅化物膜更大的厚度的第二硅化物膜。

Public/Granted literature

US20130288437A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2013-10-31

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）