Invention Grant
- Patent Title: Structure and method of wafer level chip molded packaging
- Patent Title (中): 晶圆级芯片成型包装的结构和方法
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Application No.: US12820587Application Date: 2010-06-22
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Publication No.: US08647963B2Publication Date: 2014-02-11
- Inventor: Hsin-Hui Lee , William Cheng
- Applicant: Hsin-Hui Lee , William Cheng
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/46 ; H01L21/00
Abstract:
A wafer is provided having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies are provided, each of the dies is bonded to one of the plurality of semiconductor chips. One or more trenches are formed on the chip side of the wafer. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material, the protecting material substantially filling the one or more trenches. The wafer is diced to separate it into individual semiconductor packages.
Public/Granted literature
- US20110006404A1 STRUCTURE AND METHOD OF WAFER LEVEL CHIP MOLDED PACKAGING Public/Granted day:2011-01-13
Information query
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