Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same

Invention Grant

US08647976B2 Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same 有权

Title translation: 具有在顶部和底部衬底表面上的测试焊盘的半导体封装及其测试方法

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Patent Title: Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same
Patent Title (中): 具有在顶部和底部衬底表面上的测试焊盘的半导体封装及其测试方法
Application No.: US13348767

Application Date: 2012-01-12
Publication No.: US08647976B2

Publication Date: 2014-02-11
Inventor: Eun-seok Song , Dong-han Kim , Hee-seok Lee
Applicant: Eun-seok Song , Dong-han Kim , Hee-seok Lee
Applicant Address: KR Suwon-si, Gyeonggi-do
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR Suwon-si, Gyeonggi-do
Agency: Volentine & Whitt, PLLC
Priority: KR10-2006-0085885 20060906
Main IPC: H01L21/4763
IPC: H01L21/4763

Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same

Abstract:

A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract(Chinese):

公开了半导体封装和测试方法。封装包括具有顶表面和底表面的衬底，安装在衬底的位于中心的半导体芯片安装区域中的半导体芯片以及设置在衬底的顶表面和底表面上的多个测试焊盘，并且包括第一组测试焊盘配置在衬底的顶表面和底表面上并且具有在衬底的相应顶部和底部表面上方的第一高度，以及设置在衬底的下表面上并具有大于第一衬底的第二高度的第二组测试焊盘其中第二组测试垫中的每一个包括附接到其上的焊球。

Public/Granted literature

US20120105089A1 SEMICONDUCTOR PACKAGE HAVING TEST PADS ON TOP AND BOTTOM SUBSTRATE SURFACES AND METHOD OF TESTING SAME Public/Granted day:2012-05-03

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）