Invention Grant
US08648339B2 Semiconductor device including first semiconductor chip including first pads connected to first terminals, and second semiconductor chip including second pads connected to second terminals 失效
半导体器件包括包括连接到第一端子的第一焊盘的第一半导体芯片,以及包括连接到第二端子的第二焊盘的第二半导体芯片

  • Patent Title: Semiconductor device including first semiconductor chip including first pads connected to first terminals, and second semiconductor chip including second pads connected to second terminals
  • Patent Title (中): 半导体器件包括包括连接到第一端子的第一焊盘的第一半导体芯片,以及包括连接到第二端子的第二焊盘的第二半导体芯片
  • Application No.: US12926293
    Application Date: 2010-11-08
  • Publication No.: US08648339B2
    Publication Date: 2014-02-11
  • Inventor: Takahiro KoyamaSadayuki Okuma
  • Applicant: Takahiro KoyamaSadayuki Okuma
  • Applicant Address: JP Tokyo
  • Assignee: Elpida Memory, Inc.
  • Current Assignee: Elpida Memory, Inc.
  • Current Assignee Address: JP Tokyo
  • Agency: McGinn IP Law Group, PLLC
  • Priority: JP2009-266922 20091125
  • Main IPC: H01L23/58
  • IPC: H01L23/58
Semiconductor device including first semiconductor chip including first pads connected to first terminals, and second semiconductor chip including second pads connected to second terminals
Abstract:
A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion. The second test circuit generates a second test result in response to a data output from the second memory portion, and the third test circuit generates a third test result in response to the second test result and the first test result input from the first test circuit of the first semiconductor chip and outputs the third test result from a specified second data input/output terminal.
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