Invention Grant
- Patent Title: Wafer scribe line structure for improving IC reliability
- Patent Title (中): 晶片刻划线结构,提高IC的可靠性
-
Application No.: US12054082Application Date: 2008-03-24
-
Publication No.: US08648444B2Publication Date: 2014-02-11
- Inventor: Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Yu-Wen Liu
- Applicant: Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Yu-Wen Liu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/78
- IPC: H01L21/78

Abstract:
A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.
Public/Granted literature
- US20090140393A1 WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY Public/Granted day:2009-06-04
Information query
IPC分类: