Invention Grant
US08648444B2 Wafer scribe line structure for improving IC reliability 有权
晶片刻划线结构,提高IC的可靠性

Wafer scribe line structure for improving IC reliability
Abstract:
A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.
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