Invention Grant
- Patent Title: Semiconductor interconnect structure having enhanced performance and reliability
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Application No.: US13246904Application Date: 2011-09-28
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Publication No.: US08648465B2Publication Date: 2014-02-11
- Inventor: Cyril Cabral, Jr. , Geraud Jean-Michel Dubois , Daniel C. Edelstein , Takeshi Nogami , Daniel P. Sanders
- Applicant: Cyril Cabral, Jr. , Geraud Jean-Michel Dubois , Daniel C. Edelstein , Takeshi Nogami , Daniel P. Sanders
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Abdul-Samad Adediran; Nicholas L. Cadmus
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.
Public/Granted literature
- US20130075908A1 SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY Public/Granted day:2013-03-28
Information query
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