Invention Grant
- Patent Title: Nonvolatile semiconductor memory device including a via-hole with a narrowing cross-section and method of manufacturing the same
- Patent Title (中): 包括具有窄截面的通孔的非易失性半导体存储器件及其制造方法
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Application No.: US13454625Application Date: 2012-04-24
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Publication No.: US08648471B2Publication Date: 2014-02-11
- Inventor: Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
- Applicant: Hideyuki Tabata , Eiji Ito , Hirofumi Inoue
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-303668 20071122
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L23/40

Abstract:
A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.
Public/Granted literature
- US20120205612A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2012-08-16
Information query
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