Invention Grant
US08648615B2 Testing die-to-die bonding and rework 有权
测试模具到芯片的粘合和返工

  • Patent Title: Testing die-to-die bonding and rework
  • Patent Title (中): 测试模具到芯片的粘合和返工
  • Application No.: US12824536
    Application Date: 2010-06-28
  • Publication No.: US08648615B2
    Publication Date: 2014-02-11
  • Inventor: Arifur Rahman
  • Applicant: Arifur Rahman
  • Applicant Address: US CA San Jose
  • Assignee: Xilinx, Inc.
  • Current Assignee: Xilinx, Inc.
  • Current Assignee Address: US CA San Jose
  • Agent Kevin T. Cuenot; LeRoy D. Maunu; Lois D. Cartier
  • Main IPC: G01R31/20
  • IPC: G01R31/20
Testing die-to-die bonding and rework
Abstract:
A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.
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