Invention Grant
- Patent Title: Buffer circuit
- Patent Title (中): 缓冲电路
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Application No.: US13104494Application Date: 2011-05-10
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Publication No.: US08648849B2Publication Date: 2014-02-11
- Inventor: Yoshiaki Ito
- Applicant: Yoshiaki Ito
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2010-110995 20100513
- Main IPC: G09G5/00
- IPC: G09G5/00

Abstract:
A buffer circuit having high slew rate is provided. The buffer circuit is provided, which includes a plurality of transistors having the same conductivity type and a capacitor and whose gain is determined depending on the gain of all the plurality of transistors. A buffer circuit having high driving capability and high gain of a high-frequency component can be provided. Such a buffer circuit has also high slew rate. The plurality of transistors having the same conductivity type in the buffer circuit may be either p-channel transistors or n-channel transistors.
Public/Granted literature
- US20110279438A1 BUFFER CIRCUIT Public/Granted day:2011-11-17
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