A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal.