According to one embodiment, an interface includes first to third input circuits, delay and selection circuits. The first input circuit outputs an active first internal signal in response to an active first control signal received by a memory device. The second input circuit outputs an active second internal signal in response to an active second control signal received by the device while the device is receiving the active first control signal. The delay circuit outputs a selection signal in first or second states after the elapse of a first period from inactivation or activation of the first control signal. The selection circuit outputs the first and second internal signals as an enable signal while receiving the selection signal of the first and second states. The third input circuit outputs an input signal received from the outside from the interface to inside the device while receiving the active enable signal.