Invention Grant
- Patent Title: Parallel flip-flop setup and hold timing analysis
- Patent Title (中): 并行触发器设置和保持时序分析
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Application No.: US13033961Application Date: 2011-02-24
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Publication No.: US08650021B2Publication Date: 2014-02-11
- Inventor: Kashuk Patra
- Applicant: Kashuk Patra
- Applicant Address: unknown Redwood Shores
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: unknown Redwood Shores
- Agency: Miles & Stockbridge P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A computer aided design system determines the acceptable timing for a flip-flop cell. The system generates a search window having a pass edge and a fail edge and divides the search window into four sections using three quadsection values. For each of the quadsection values, the system simulates a timing analysis of the flip-flop and determines if each of the quadsection values pass or fail the analysis. The analysis may be done in parallel. If at least one of the quadsection values passes the analysis, the system causes one of the passed quadsection values to be a new pass edge for the search window. If at least one of the quadsection values fails the analysis, the system causes one of the failed quadsection values to be a new fail edge for the search window. If the search window is less than a predetermined window width, the system assigns the new pass edge as the determined timing. If the search window is not less than the predetermined window width, the system repeats the above, starting with dividing the new search window into four sections using three quadsection values.
Public/Granted literature
- US20120221313A1 PARALLEL FLIP-FLOP SETUP AND HOLD TIMING ANALYSIS Public/Granted day:2012-08-30
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