In the field of integrated circuit (IC) design, a method and a bus system for equalizing data information traffic and a decoder are provided. The method includes: receiving data information sent by a device, and allocating at least two transmission interfaces for the data information according to a decoding result of decoding a designated bit in the data information, where the data information carries a device ID, and the designated bit position occupied at least one bit in the device ID; judging whether the data information traffic of the at least two transmission interfaces is balanced; and when the data information traffic of the at least two transmission interfaces is not balanced, switching the designated bit position, and decoding the designated bit after switching, so as to balance the traffic of the at least two transmission interfaces. The bus system includes an interface allocation module, a traffic judging module and a bit position switching module. The decoder includes a decoding module and a designated bit position switching module.