A processor has a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address. The processor determines, when a target logical address accessed by one of threads is translated to the physical address, whether an entry corresponding to the target logical address is present in the first table, the target logical address is of a page accessed by a program. The processor determines, when the entry corresponding to the target logical address is not present in the first table, whether the target logical address has been accessed during the running of the program. The processor delays, when the target logical address has not yet been accessed, the process of reading the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread.