Invention Grant
- Patent Title: Universal chip carrier and method
- Patent Title (中): 通用芯片载体和方法
-
Application No.: US13106383Application Date: 2011-05-12
-
Publication No.: US08650748B2Publication Date: 2014-02-18
- Inventor: Artur Darbinyan , David T. Chin , Kurt E. Sincerbox
- Applicant: Artur Darbinyan , David T. Chin , Kurt E. Sincerbox
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Eugene C. Conser; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H05K3/30
- IPC: H05K3/30

Abstract:
A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.
Public/Granted literature
- US20120285730A1 UNIVERSAL CHIP CARRIER AND METHOD Public/Granted day:2012-11-15
Information query